1. Field of the Invention
The present invention generally relates to a method for producing a semiconductor device, and more particularly to a method for improving uniformity of a chemical mechanical polishing (CMP) operation used in producing the semiconductor device.
2. Description of the Related Art
Conventional systems utilize shallow trench isolation (STI) in advanced integrated circuits to electrically isolate neighboring devices. Chemical mechanical polishing (CMP) is often used to pattern insulators in semiconductor trenches or conductors in insulating trenches. In many applications, the polishing is stopped only after all the material has been removed from the field regions.
However, oftentimes this operation results in over-polishing of the material in wide trenches.
For example, FIGS. 1A-1D illustrate a conventional process which is relatively simple, and is extendable to sub-quarter micron dimensions. In FIG. 1A, a pad oxide 11 is grown by thermal oxidation of a silicon substrate 10. Thereafter, a pad nitride, formed for example of SiN 12, is deposited on the SiO.sub.2 layer. Then, the trenches are etched.
In FIG. 1B, a SiO.sub.2 layer 14 is deposited to fill the trenches.
In step 1C, the SiO.sub.2 layer 14 is patterned by CMP.
Finally in step 1D, the pad nitride and pad oxide are stripped, and a sacrificial oxide 15 is grown.
However, a problem with the conventional process is that the polishing process used to pattern the SiO.sub.2 isolation, as shown in FIG. 1C, may result in localized variations in the SiO.sub.2 thickness. This is a problem, and could result in the resulting device "failing" during operation.
That is, in regions where the trenches are wide or the density of the active area is low, such as in region C of FIG. 1D, there is excessive thinning of the SiO.sub.2. The excessive oxide thinning allows the gate to wrap around the active areas, resulting in a low threshold voltage for the affected devices. Again, this may cause the device(s) to fail.
Moreover, in regions where the active areas are wide or where there is a low density of trenches, there may be insufficient removal of the SiO.sub.2 such as in region A in FIG. 1D. The residual SiO.sub.2 masks the pad nitride strip, and the pad nitride blocks subsequent implants and gate oxide growth, resulting in failing devices.
Localized variations in polishing resulting from variations in the pattern factor are also observed for other CMP processes. For example, such processes include metal CMP to produce damascene interconnects (e.g., see FIGS. 3A-3C described below) or studs, dielectric planarization over a gate stack (e.g., see FIGS. 5A-5C described below) or a metal stack, and polysilicon patterning in deep trenches.
In the case of metal CMP, there is generally an excessive removal of metal in regions with wide metal features (e.g., region C in FIG. 3C), whereas there may be insufficient removal of metal in wide oxide regions (e.g., see region A in FIG. 3C). The excessive thinning of metal results in high resistance, and increased circuit delays. The residual metal on top of the oxide can result in leakage between interconnects.
Thus, the conventional processes result in poor local uniformity of CMP of SiO.sub.2 isolations and other structures. As a result, the devices produced may suffer failures.